1. Field of the Invention
The present invention concerns a method of producing an electro-optical device in which thin film transistors are formed and, more in particular, it relates to a technique capable of reducing the number of photolithographic steps as compared with that in the prior art method.
2. Description of the Related Art Statement
FIG. 165 shows an example for a constitution of an equivalent circuit of an active matrix liquid crystal display device using thin film transistors as switching elements.
In FIG. 169, a plurality of gate wirings G1, G2, - - - , Gn and a plurality of source wirings S1, S2, - - - , Sm are wired in a matrix, in which each of the gate wirings G is connected to a scanning circuit 1 and each of the signal wirings S is connected to a signal supply circuit 2 respectively. A thin film transistor (switching element) 3 is disposed to a crossing point between each of the wirings and a capacitance section 4 as a capacitor and a liquid crystal device 5 are connected to a drain electrode of the thin film resistor 3 to constitute a circuit.
FIG. 170 and FIG. 171 illustrate an example for a structure of a thin film transistor array substrate having portions, for example, the gate wirings G and the source wirings F on a substrate in an existent active matrix liquid crystal display device shown by the equivalent circuit in FIG. 169.
In the thin film transistor array substrate shown in FIG. 170 and FIG. 171, the gate wirings G and the source wirings S are wired in a matrix on a transparent substrate 6 such as made of glass. Further, a thin film resistor 3 is disposed near the crossing point between each of the gate wirings G and the source wirings S.
The thin film transistor 3 shown in FIG. 170 and FIG. 171 has a general etch-stopper type constitution formed by disposing an gate insulator film 9 on the gate wiring G and a gate electrode 8 led out of the gate wiring G, disposing a semiconductor film 10 made of amorphous silicon (a-Si) on the gate insulator film 9 and further disposing, on the semiconductor film 10, a drain electrode 11 and a source electrode 12 made of an electroconductive material opposing to each other. An ohmic contact film 10a comprising, for example, amorphous silicon and doped at a high concentration with an impurity as such as phosphorus as a doner is formed to the uppermost layer of the semiconductor film, on which an etching stopper 13 is formed being put between the drain electrode 11 and the source electrode 12. Further, the gate electrode 8 has a double structure comprising a gate insulator film 8a of an upper layer and a gate wiring 8b of a lower layer, and a transparent pixel electrode 15 made of a transparent electrode material is formed from a portion above the drain electrode 11 to lateral sides of the drain electrode 11.
Then a passivation film 16 is disposed covering, for example, the gate insulator film 9, the transparent pixel electrode 15 and the source electrode 12.
A not illustrated orientation film is formed on the passivation film 16, and liquid crystals are disposed above the orientation film to constitute an active matrix liquid crystal display device 15 and the device can control the orientation of liquid crystal molecules when an electric field is applied to the molecules of the liquid crystals by way of the transparent pixel electrode 15.
By the way, the thin film transistor array substrate of the structure described above has been produced so far based on the steps as described in Table 1 shown below.
TABLE 1 __________________________________________________________________________ Step Production method Material Remarks __________________________________________________________________________ Initial cleaning Brush and UV Formation of surface stabilization layer Reactive sputtering TaOx 750 nm Formation of gate wiring metal DC sputtering Al 200 nm Gate wiring metal PL 1 Wet etching Formation of gate electrode DC sputtering Ta 400 nm Gate electrode PL 2 Dry etching Anodization of gate electrode TaOx 300 nm Formation of gate insulation Plasma CVD SiNx 250 nm Formation of a-Si Plasma CVD a-Si 50 nm Formation of ES insulator layer Plasma CVD SiNx 100 nm ES insulator layer PL 3 Wet etching Back exposure method Formation of SD semiconductor Plasma CVD n + Si 25 nm Device area PL 4 Dry etching Formation of SD electrode DC sputtering Ti 400 nm SD electrode PL 5 Dry etching Formation of transparent electrode Reactive sputtering ITO 50 nm Transparent electrode PL 6 Wet etching Formation of protection layer Plasma CVD SiNx 250 nm Protection layer PL 7 Wet etching __________________________________________________________________________ Note: PL: photolithography, ES: etching stopper, SD: source/drain 1-7: Exposure process
At first, a transparent substrate, for example, made of glass is prepared, and then put to initial cleaning by a brush cleaning device and an UV-irradiation device, and a surface stabilization film, for example, made of TiO.sub.x is formed by using a film-forming method such as reactive sputtering on the transparent substrate after cleaning.
A metal film for gate wirings made of an electroconductive material such as Al is deposited on the substrate formed with a surface stabilization film by using a film forming-method such as DC sputtering, and the metal film is etched in a first photolithographic step (1) using a method such as wet etching, to form gate wirings.
Then, a metal film for forming a gate electrode made, for example, of Ta is deposited on the gate wirings by a film forming method such as DC sputtering and then the metal film is etched in a second photolithographic step (2) using a method such as dry etching, to form the gate electrode.
Then, the gate electrode is anodized to form the surface portion into TaO.sub.x to apply a treatment for improving the insulation performance of the gate electrode.
Successively, a gate insulator film made of SiN.sub.x, a semiconductor film made of a-Si (amorphous silicon) or the like and an insulator film for etching stopper made of SiN.sub.x are formed on them by a film-forming method such as plasma CVD.
Then, etching is applied in a third photolithographic step (3) using a method, for example, of wet etching to form an etching stopper on the gate electrode.
Then, an ohmic contact film such as made of a-Si(n.sup.+) is formed on the surface of the substrate after the third photolithographic step by using a method such as plasma CVD.
Then, the semiconductor film and the ohmic contact film are patterned in a fourth photolithographic step (4) using a method such as DC sputtering to form a semiconductor portion above the gate electrode in a state isolated from other portions.
Then, a metal film made, for example, of Ti is formed on the surface of the substrate after the fourth photolithographic step by using a film-forming method such as DC sputtering.
Then, the metal film is patterned in a fifth photolithographic step (5) using a method such as dry etching to form a source electrode and a drain electrode.
Then, a transparent conductive film, for example, made of ITO (Indium Tin Oxide) is formed on the surface of the substrate after the fifth photolithographic step by a film-forming method such as reactive sputtering.
Then, the transparent conductive film is fabricated in a sixth photolithographic step (6) using a method such as wet etching to form a transparent pixel electrode, and then
a protection film, for example, made of SiN.sub.x is formed on the surface of the substrate after the sixth photolithographic step by a method such as plasma CVD. PA1 a step A1 for forming a transparent conductive film on the surface of the substrate, PA1 a first photolithographic step A2 of patterning the transparent conductive film to form a transparent pixel electrode, PA1 a step A3 of forming a first metal film on the surface of the substrate after the first photolithographic step, PA1 a third photolithographic A4 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step A5 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step A6 of patterning the first insulator film, the semiconductor active film and the ohmic contact film to form a contact hole reaching the transparent pixel electrode and a contact hole reaching the gate wiring, PA1 a step A7 of forming a second metal film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step A8 of patterning the second metal film, to form a source electrode, a source wiring, a drain electrode connected with the transparent pixel electrode by way of the contact hole reaching the transparent pixel electrode and a gate terminal wiring connected with the gate wiring by way of the contact hole reaching the gate electrode, and fabricating the ohmic contact film by using the second metal film as a mask to form a channel portion above the gate electrode, PA1 a step A9 of forming a passivation film on the surface of the substrate after forming the channel portion, and PA1 a fifth photolithographic step A10 of forming, to the passivation film, a contact hole reaching the gate terminal wiring and the source wiring, and fabricating the semiconductor active film below the source electrode, the drain electrode and the source wiring using the passivation film as a mask to isolate the same from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and make a portion above the pixel electrode light permeable. PA1 the step A3 of forming the first metal film on the surface of the substrate and PA1 the second photolithographic step A4 of patterning the first metal film to form the gate electrode and the gate wiring are conducted and, subsequently, PA1 the step Al of forming the transparent conductive film on the surface of the substrate and PA1 the first photolithographic step A2 of patterning the transparent conductive film to form the transparent pixel electrode are applied. PA1 a step B1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step B2 of patterning the first metal film to form a gate electrode and a gate wiring, a step B3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step B4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step B5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step B6 of forming a transparent conductive film for a transparent pixel electrode, a second metal film for a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step B7 of patterning the second metal film, the transparent conductive film and the semiconductor active film and the ohmic contact film to form a source electrode, a source wiring and a drain electrode and, further, forming a channel portion above the gate electrode and forming a transparent pixel electrode, PA1 a step B8 of forming the passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step B9 of patterning the passivation film and the second metal film to make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step C1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step C2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step C3 of forming a first insulator film, a semiconductor active film, an ohmic contact film and a metal film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step C4 of patterning the semiconductor active film, the ohmic contact and the metal film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step C5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step C6 of forming a transparent conductive film for a transparent pixel electrode, a source electrode and a drain electrode on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step C7 of patterning the transparent conductive film to form a source electrode, a source wiring, a drain electrode and a transparent pixel electrode, and patterning the transparent conductive film, the buffer film and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, PA1 a step C8 of forming a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step C9 of patterning the passivation film to remove a portion of the passivation film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step D1 of forming a transparent conductive film for a transparent pixel electrode and a first film for a gate electrode and a gate wiring on the transparent conductive film on the surface of the substrate, PA1 a first photolithographic step D2 of patterning the transparent conductive film and the first metal film to form a gate electrode, a gate wiring and a transparent pixel electrode, PA1 a step D3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step D4 of patterning the ohmic contact film, the semiconductor active film and the first insulator film to form a contact hole reaching the gate wiring, PA1 a step D5 of forming a second metal film for the source electrode and the drain electrode on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step D6 of patterning the second metal film to form the source electrode and the drain electrode and patterning the second metal film and the ohmic contact film on the gate electrode to form a channel portion above the gate electrode, PA1 a step D7 of forming a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step D8 of patterning the passivation film to remove a portion of the passivation film, the second metal film, the ohmic contact film, the semiconductor active film and the first insulator film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable, isolating the semiconductor active film below the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistor having the gate wiring in common and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step E1 of forming a transparent conductive film for a transparent pixel electrode and a first film for a gate electrode and a gate wiring on the transparent conductive film on the surface of the substrate, PA1 a first photolithographic step E2 of patterning the transparent conductive film and the first metal film to form a gate electrode, a gate wiring and a transparent pixel electrode, PA1 a step E3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step E4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a third photolithographic step E5 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step E6 forming a second metal film for a source electrode and a drain electrode on the surface of the substrate after the third lithographic step, PA1 a fourth photolithographic step E7 of patterning the second metal film to form a source electrode and a drain electrode, and patterning the second metal film and the ohmic contact film above the gate electrode to form a channel portion above the gate electrode, PA1 a step E8 of forming a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step E9 of patterning the passivation film to remove a portion of the passivation film, the second metal film and the first insulator film above the transparent pixel electrode and make a portion above the transparent pixel electrode light permeable, and forming a contact hole for source wiring and gate wiring connection terminal. PA1 a step F1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step F2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step F3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step F4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step F5 of forming a transparent conductive film, a second metal film and an ohmic contact film in this order on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step F6 of patterning the ohmic contact film, the second metal film and the transparent conductive film to form a source electrode, a drain electrode, a channel portion and a transparent pixel electrode, PA1 a step F7 of forming a semiconductor active film and a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step F8 of patterning the passivation film, the semiconductor active film, the ohmic contact film and the second metal film to make a portion above the transparent pixel electrode light permeable and isolate the semiconductor film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole for source wiring and gate wiring connection terminals. PA1 a step G1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step G2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step G3 of forming a first insulator film, a semiconductor film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step G4 of patterning the semiconductor active film and the ohmic contact film to form a semiconductor portion above the gate electrode in a state isolated from other portions, PA1 a step G5 of forming a second metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step G6 of patterning the second metal film and the ohmic contact film to form a source electrode, a drain electrode and a channel portion, PA1 a step G7 of forming a passivation film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step G8 of patterning the passivation film to form a contact hole reaching the gate wiring, a contact hole reaching the drain electrode and a contact hole for source wiring and gate wiring connection terminals, PA1 a step G9 forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step G10 of patterning the transparent conductive film to form a transparent pixel electrode. PA1 a step H1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step H2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step H3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step H4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step H5 of forming a second metal film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step H6 of patterning the ohmic contact film and the second metal film to form a source electrode, a drain electrode, a source wiring and a channel portion, PA1 a step H7 of forming a semiconductor active film and a passivation film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step H8 of patterning the passivation film, the semiconductor active film and the ohmic contact film to make a transparent pixel electrode area light permeable, isolating the semiconductor active film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole reaching the source wiring, PA1 a step H9 forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step and PA1 a step H10 of patterning the transparent conductive film to form a transparent pixel electrode. PA1 a step J1 of forming a first metal film on the surface of the substrate, PA1 a first photolithographic step J2 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step J3 of forming a first insulator film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step J4 of patterning the first insulator film to form a contact hole reaching the gate wiring, PA1 a step J5 of forming a transparent conductive film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step J6 of patterning the transparent electrode to form a source electrode, a drain electrode, a source wiring and a channel portion, PA1 a step J7 of forming a second metal film and an ohmic contact film in this order on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step J8 of patterning the ohmic contact film, the second metal film and the ohmic contact film to form a source electrode, a drain electrode and a channel portion, PA1 a step J9 of forming a semiconductor film and a passivation film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step J10 of patterning the passivation film, the semiconductor active film, the ohmic contact film and the second metal film to make a portion above the transparent pixel electrode light permeable, isolating the semiconductor active film above the source electrode, the drain electrode and the source wiring from the semiconductor active film of adjacent thin film transistors having the gate wiring in common and forming a contact hole reaching the source wiring. PA1 a step L1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step L2 of patterning the light screening thin film to form a light screening film, PA1 a step L3 of forming a first insulator film and a semiconductor active film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step L4 of patterning the semiconductor active film to form a semiconductor portion on the light screening film, PA1 a step L5 of forming a second insulator film and a first metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step L6 of patterning the first metal film to form a gate electrode and a gate wiring, PA1 a step L7 of forming a third insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step L8 of patterning the second insulator film and the third insulator film to form a contact hole reaching one end of the semiconductor portion and a contact hole reaching the other end of the semiconductor portion, and patterning the third insulator film to form a contact hole reaching the gate wiring, PA1 a step L9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step L10 of patterning the transparent conductive film to form a source electrode, a source wiring and a drain electrode on both sides of the gate electrode and forming a pixel electrode. PA1 a step M1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step M2 of patterning the light screening thin film to form a light screening film, PA1 a step M3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step M4 of patterning the ohmic contact film and the semiconductor active film to form a semiconductor portion above the light screening film, PA1 a step M5 of forming a first metal film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step M6 of patterning the first metal film to form a source electrode, a drain electrode and a source wiring, PA1 a step M7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step M8 of patterning the second insulator film to form a contact hole reaching gate wiring, a contact hole reaching the source wiring and a contact hole reaching the drain electrode, PA1 a step M9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step M10 of patterning the transparent conductive film to form a gate electrode above a portion between the source electrode and the drain electrode and forming a gate wiring in connection with the gate electrode. PA1 a step N1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step N2 of patterning the light screening thin film to form a light screening film, PA1 a step N3 of forming a first insulator film, a semiconductor active film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step N4 of patterning the ohmic contact film and the semiconductor film to form a semiconductor portion above the light screening film, PA1 a step N5 of forming a transparent conductive film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step N6 of patterning the transparent conductive film to form a source electrode, a drain electrode, a source wiring and a pixel electrode, PA1 a step N7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step N8 of patterning the second insulator film to form a contact hole for gate wiring and a source wiring connection, PA1 a step N9 of forming a metal film on the surface of the substrate after the fourth photolithographic step, and PA1 a fifth photolithographic step N10 of patterning the metal film to form a gate electrode above a portion between the source electrode and the drain electrode and forming a gate wiring in connection with the gate electrode. PA1 a step O1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step O2 of patterning the light screening thin film to form a light screening film, PA1 a step O3 of forming a first insulator film, a first metal film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step O4 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion, and forming a source electrode, a drain electrode and a source wiring above the light screening film, PA1 a step O5 of forming a semiconductor active film and a passivation film protecting the same on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step O6 of patterning the passivation film, the semiconductor active film and the ohmic contact film to form a semiconductor portion and forming contact hole for connecting the gate wiring and the source wiring, PA1 a step O7 of forming a transparent conductive film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step O8 of patterning the transparent conductive film to form a gate electrode above a portion between the source electrode and the drain electrode and form a pixel electrode. PA1 a first photolithographic step P2 of patterning the light screening thin film to form a light screening film, PA1 a step P3 of forming a first insulator film, a transparent conductive film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step P4 of patterning the ohmic contact film and the transparent conductive film to form a n.sup.+ semiconductor channel portion, and forming a source electrode, a drain electrode, a source wiring and a pixel electrode above the light screening film, PA1 a step P5 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step P6 of patterning the second insulator film, the semiconductor active film and the ohmic contact film to form a contact hole for connecting the gate wiring and the source wiring, PA1 a step P7 of forming a metal film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step P8 of patterning the metal film to form a gate electrode above a portion between the source electrode and the drain electrode and removing a film above the pixel electrode. PA1 a step Q1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step Q2 of patterning the light screening thin film to form a light screening film, PA1 a step Q3 of forming a first insulator film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step Q4 of patterning the transparent conductive film to form a pixel electrode, a step Q5 of forming a first metal film and an ohmic contact film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step Q6 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion above the screening film and forming a source electrode, a drain electrode and a wiring therefor, PA1 a step Q7 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step Q8 of patterning the second insulator film, the semiconductor conductive film and the ohmic contact film to form a semiconductor portion and removing the semiconductor active film and the second insulator film above the pixel electrode and, further, forming a contact hole for connecting the gate wiring and the source wiring, PA1 a step Q9 of forming a second metal film on the surface of the substrate after the fourth photolithographic step, and PA1 a step Q10 of patterning the second metal film to form a gate electrode and a wiring therefor above a portion between the source electrode and the drain electrode, and removing the second metal film above the pixel electrode and at the periphery of the semiconductor. PA1 a step R1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step R2 of patterning the light screening thin film to form a light screening film, PA1 a step R3 of forming a first insulator film, a first metal film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step R4 of patterning the ohmic contact film and the first metal film to form a semiconductor channel portion on the light screening film and, further, forming a source electrode, a drain electrode and a source wiring, PA1 a step R5 of forming a semiconductor active film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step R6 of patterning the semiconductor active film to form a semiconductor portion above the light screening film, PA1 a step R7 of forming a second insulator film on the surface of the substrate after the third photolithographic step, PA1 a fourth photolithographic step R8 of patterning the second insulator film to form a contact hole for connecting the gate wiring and the source wiring and a contact hole for connecting the drain electrode and the pixel electrode on both sides of the semiconductor portion, PA1 a step R9 of forming a transparent conductive film on the surface of the substrate after the fourth photolithographic step, and PA1 a step R10 of patterning the transparent conductive film to form a gate electrode above the semiconductor portion, and forming a gate electrode wiring and forming a pixel electrode. PA1 a step S1 of forming a light screening thin film on the surface of the substrate, PA1 a first photolithographic step S2 of patterning the light screening thin film to form a light screening film, PA1 a step S3 of forming a first insulator film, a transparent conductive film and an ohmic contact film on the surface of the substrate after the first photolithographic step, PA1 a second photolithographic step S4 of patterning the ohmic contact film and the transparent conductive film to form a semiconductor channel portion above the light screening film and, further, forming a source electrode, a drain electrode and a wiring therefor and a pixel electrode, PA1 a step S5 of forming a semiconductor active film and a second insulator film on the surface of the substrate after the second photolithographic step, PA1 a third photolithographic step S6 of patterning the second insulator film and the semiconductor active film to form a semiconductor portion, and forming a contact hole for connecting the gate wiring and the source wiring, PA1 a step S7 of forming a metal film on the surface of the substrate after the third photolithographic step, and PA1 a fourth photolithographic step S8 of patterning the metal film to form a gate electrode and a wiring therefor above the semiconductor portion and isolating the semiconductor portion with respect to each of the pixel electrodes.
Then, a seventh photolithographic step (7) of patterning the protection film by a method such as wet etching to form a contact hole for a source terminal for connection with the source electrode and a contact hole for a drain terminal for connection with the drain electrode, to complete the thin film transistor array substrate.
However, when the thin film transistor array substrate is produced by the method as described above, photolithographic steps have to be applied for seven times and, since there are a number of photolithographic steps, they give a significant effect by so much on the yield to bring about a problem of increasing the production cost.
Then, in a case of producing the thin film transistor array substrate of this type, it may be adopted a structure in which various thin films are stacked, a contact hole is formed to a portion of the laminate film, and a conductive film is formed to the contact hole to electrically connect the film of the upper layer with the film of the lower layer by way of the conductive film.
FIG. 172 shows an example of such a structure in which an insulator film 18 made, for example, of SiN.sub.x and a conductive oxide film 19 made of ITO are stacked on a metal film 17, for example, made of Ti formed on the substrate, and the conductive oxide film 19 is connected with the metal film 17 by way of a contact hole 18a formed to the insulator film 18.
In the structure of this example, the contact hole 18a is formed by a method of forming the insulator film 18, depositing thereover a predetermined pattern of a photoresist, etching the insulator film 18 by dry etching using, for example, SF.sub.6 +O.sub.2 gas to form the contact hole 18a, and then peeling off the photoresist with O.sub.2 plasma and subsequently forming the conductive oxide film 19. However, since the metal film 17 is exposed through the contact hole 18a to an oxidative atmosphere in the course of the process, there is a worry that the metal film 17 is oxidized.
In view of the above, Ti has been used so far as a metal capable of providing a good contact with the conductive oxide film 19 and is less oxidized by the O.sub.2 plasma atmosphere but a thin film of Al or Ta which is oxidized more readily than Ti can not be used, so that the material used for the metal film 17 suffers from restriction. By the way, in a case where a contact area of the connection portion is set to 7 um.sup.2 and a contact chain of a structure having 1,600 steps for the contact portion of the structure shown in FIG. 172 is formed, the contact resistance of the thin Al film to the thin ITO film is from 10.sup.10 -10.sup.12 ohm, whereas the contact resistance of the Ti thin film to the ITO thin film is from 10.sup.4 to 10.sup.5 ohm and the Ti thin film is apparently superior in the contact performance. It is considered that exposure to the O.sub.2 plasma atmosphere forms oxide layers at the boundary of the connection portion and, even if Ti has lower conductivity as compared with that of Al, it contrarily shows less contact resistance than the latter due to the presence of the oxide layers.
Further, in a case of using the thin Ti film as the metal film 17 described above, if the structure is applied to a thin film transistor array substrate to form gate wirings with the metal film 17, the Ti metal film 17 can be served for usual application use but it may possibly cause signal delay in the gate wirings since the specific resistivity of Ti itself is high, to result in a disadvantage in view of increase for the size of a liquid crystal panel.